1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device configured so that a plurality of NAND strings are connected to each bit line.
2. Description of the Related Art
For example, NAND non-volatile memory devices have conventionally been formed with one active area AA (element isolation region) for each one bit line as shown in FIG. 6, and one row of NAND strings are controlled by the active area AA. In FIG. 6, reference symbol “SG” designates a selective gate, “WL” a word line, “CB” a forming region of a bit line contact. The active area AA includes a source/drain diffusion layer of a MOS transistor and a channel region.
With progress in high integration and refinement of a memory cell, an element isolation region has recently been narrowed and it has become difficult to ensure a forming region of a bit line contact CB. JP-A-H06-325581 discloses an arrangement of non-volatile semiconductor memory device to overcome the above-noted technical problem. According to the disclosed arrangement, two rows of NAND strings are formed so as to correspond to one bit line contact. Consequently, a forming region of a bit line contact which can be ensured corresponds to a total width of two rows of NAND strings, whereupon the bit line contact can readily be formed even when a conventional process is applied.
In a NAND non-volatile semiconductor memory device with two rows of NAND strings provided so as to correspond to one bit line, two selective gate transistors are provided for each NAND string. When each selective gate transistor is configured so that a threshold voltage differs between rows and columns, either one or any one of the NAND strings can be selected. In order that the NAND non-volatile semiconductor memory device may be arranged into such a configuration, when impurities are implanted during the forming of a selective gate transistor, dose is adjusted and ion implantation is then carried out, whereby a threshold voltage of the MOS transistor differs between rows and columns of NAND strings.
FIG. 7 shows an example of the above-described arrangement. A selective gate transistor as shown in FIG. 7 includes enhancement mode MOS transistors TrE and depletion mode MOS transistors TrD both of which are formed alternately. Reference symbol “W” in FIG. 7 designates a width of the word line WL, namely, a gate length of each MOS transistor. Each of the MOS transistors TrE and TrD can be formed by adjusting an amount of ion implantation of impurities (dose).
Conventionally, in a NAND non-volatile semiconductor memory device with two rows of NAND strings provided so as to correspond to one bit line, when impurities are ion-implanted in the forming of each selective gate transistor, dose is adjusted and ion implantation is then carried out, whereby a threshold voltage of the MOS transistor differs between rows and columns of NAND strings. However, when the design rule is rendered more strict, adjusting dose and then carrying out ion implantation becomes difficult due to misalignment of a mask. Moreover, since dopant is unnecessarily diffused during a thermal process, there is a possibility that memory cells and selective gate transistors in the vicinity of the diffused layer would adversely be affected.